1. Field of the Invention
This invention relates in general to the control circuitry for CD-ROM drives, and in particular to the main controller circuitry for CD-ROM drives employing DRAM to provide working memory space for implementing signal decoding operations. More particularly, the invention relates to the main controller circuitry for CD-ROM drives with reduced access frequency in the DRAM working memory for improved overall system performance that can be implemented as a single-chip IC for reduced cost.
2. Technical Background
Laser disk drive is a category of digital storage devices widely employed in computer systems, in particular, microprocessor-based personal computers, home computers and office computer systems. In the description of this specification, these laser-based digital storage devices are generally referred to as optical disk drives, or simply as drives, as is customary in the field.
The Philips/Sony CD (Compact Disc) player is categorized as a laser technology-based optical disk drive. The CD itself has evolved from its originally intended use as a storage media for musical performances into several variants for the digital storage of information in various formats. Large amounts of digital information can be recorded on the surface of discs with 12-cm diameter. Different applications have been developed based on different formats of these CD variants. For example, in addition to the original music CD player, CD drives known as the CD-ROM drives have become widely used in the personal computer industry. Modularized designs of the CD-ROM drive can be installed in the expansion bays of typical personal computer systems such as the IBM-compatibles and serve the purpose of mass data storage at low cost.
The CD-ROM disc media used widely in the personal computer industry is one that complies with the ISO-9660 standard capable of holding more than 650 MB of information. In addition to the retrieval of data contained in the CD-ROM discs, current CD-ROM drives are also capable of playing music CDs, as well as multimedia VCDs. CD-ROM drives have virtually become the standard subsystem for personal computers.
Due to the wide acceptance of CD-ROM drives in personal computer systems, severe competition has built up in the CD-ROM drive manufacturing business. The direct result of this business competition is the rapid reduction in prices as well as rapid increase in performances. For the purpose of storage of files and/or high-resolution image/video information such as the lately established DVD (Digital Video Disc), the advancements in microprocessor technology has also urged increased demand for ever larger amounts and faster speeds of information storage and retrieval. For example, while a music CD player operates at its standard spindle speed of more than 100 to about 300 rpm, CD-ROM drives have evolved through 2.times. (double the spindle speed), 4.times., 6.times., 8.times., and eventually up to 10 and even faster speeds. For the purpose of data retrieval, this increased spindle speed effectively improves the drive data transfer rate.
The digital electronic control circuitry used in the conventional CD-ROM drives usually includes an IC chip-set of two separate chips. One of the two being the read controller IC, and the other the signal decoder IC. The read controller IC includes an internal SRAM with a memory space of about 2 K bytes that is used as the data manipulation space for the de-interleaving operation. The signal decoder, on the other hand, controls an external DRAM device for implementing memory caching during operation.
Since the two IC chips are physically separate, therefore, the internal SRAM in the read controller IC is indispensable. If the two are fabricated into one single IC, and the DRAM memory device is used to replace the internal SRAM of the read controller IC, the access frequency to the DRAM would inevitably be increased to an impractical level. This is because DRAM is inherently much slower than SRAM in operating speed, which is a fact leading to the formation of a bottleneck in such a single-chip design.
In order to describe the invention, configuration of the digital electronic controlling circuitry of a conventional CD-ROM is briefly examined below. FIG. 1 is a block diagram showing the circuit configuration of the digital control electronics of a conventional CD-ROM drive. As is shown in the block diagram, the circuitry includes a read access controller 120, a signal decoder 130, an RF (radio frequency) amplifier 110 and a DRAM 140. All these circuit elements are organized and connected in a wiring network. Also note that a laser pick-up head 103 as well as a disk spindle motor 102 are also shown in the drawing and are included in the drive. These are opto- and electro-mechanical components of the drive mechanism controlled by the read access controller 120.
In the prior-art technique, the circuit elements of FIG. 1 can each be implemented as separate IC chips. For example, before being assembled into a controller electronic circuitry, the DRAM 140 can be an independent memory IC chip, the RF amplifier 110 an independent RF IC, and the read access controller 120 and the signal decoder 130 may also be physically independent from each other.
In the case of the circuitry configuration of FIG. 1, operation of the conventional CD-ROM drive concerning a host computer system such as a personal computer accessing the CD-ROM is described as follows. The spindle motor 102 spins the CD-ROM disc 101, and the laser pick-up head 103 retrieves data recorded in the form of small pits formed into the surface of the disc 101. Data pick up by the head 103 is then relayed to the RF amplifier 110 via connection 4. After amplification, portions of the data are then sent to the DSP (digital signal processor) 121 in the read access controller 120 via connection 5. DSP 121 then processes its received data, and controls the disc spindle motor 102 via the connection 7 based on its obtained data in order to maintain the spindle 102 at the proper rotational speed. On the other hand, the DSP 121 also controls the laser pick-up head 103 via the connection 6 to achieve precision adjustment over the drive mechanism in order to obtain adequate beam-focusing as well as proper head-tracking.
In addition to being sent to the DSP 121 via the connection 5 for servo control, the devised RF signal is further sent to the demodulation unit 122 of the read access controller 120 for implementing the decoding of the EFM (Eight-to-Fourteen Modulation encoding) code. In the EFM demodulation unit 122, a digital signal is extracted from the RF signal, and demodulated in accordance with the stipulations of the IEC (International Electrotechnical Commission) 908 standard. The result of this EFM demodulation are data signals arranged in bytes that can be sent to the CIRC (Cross-Interleave Reed-Solomon) decoder 123 for decoding of the Reed-Solomon code.
The CIRC decoder 123 also performs error detection and correction (EDC) as well as de-interleaving operations in accordance with the IEC 908 standard. In order to implement de-interleaving and also serve as a data buffer when receiving the input data, the CIRC decoder 123 must have a configuration incorporating a memory space sufficient for data manipulation during the process of operation. This memory space is normally a 2 K-byte SRAM 124 as included in the drawing.
After error detection and de-interleaving processing, data can be converted into serial form in the serial output unit 125, and then sent to the next processing circuit, namely the signal decoder 130 via the connection 26.
The signal decoder 130 proceeds with its error detection and correction operations utilizing the internal RSPC (Reed-Solomon product-like code) decoder 132 in accordance with the stipulations of the ISO/IEC 10149 standard. This is done by the RSPC decoder 132 performing an operation on the serial data received by the signal decoder 130 over connection 26. Then, the EDC generation unit 134 of the signal decoder 130 performs data error detection in terms of data blocks. If any error is detected, the correction procedure can be invoked to correct. After being processed by the EDC generation unit 134, data can then be relayed to the IDE or SCSI interface of the CD-ROM drive and then to the bus 150 under the control of the interface unit 133. Thus, data is then accessible by the host computer system over the bus 150.
In such conventional CD-ROM drives, one of the differences between the read access controller 120 and the signal processor 130 is that signal processor 130 needs to use cache memory for its operation. As the data access speed of CD-ROM drives are becoming ever faster a, data cache scheme in the data-decoding mathematical operations has become indispensable. However, cache hit rates in a caching memory is directly related to the size of the cache memory. In other words, too small a caching area is unable to achieve meaningful hit rates. As a result, since the 2 K-byte SRAM memory space is too small to be effective for providing useful caching space for the signal processor 130 to use, therefore, an additional external memory device such as a DRAM 140 is required. In this case, all units including EDC generation unit 134, RSPC unit 132 and interface controller unit 133 utilize the external DRAM 140 instead of their corresponding internal small SRAM as the working space, as the read access controller 120 has its own internal small SRAM 124.
In FIG. 1, both the internal SRAM 124 of read access controller 120 and the external DRAM 140 of the signal decoder 130 will experience substantially proportional increased frequency of access as the CD-ROM spindle speed is increased. Therefore, when designing the control electronics of a CD-ROM drive, the allowed highest access speed of both the SRAM 124 and the DRAM 140 must also be increased as the CD-ROM drive spindle speed is improved.
The following analysis calculates the frequency of access into the corresponding SRAM 124 and DRAM 140 by the read access controller 120 and the signal decoder 130 respectively as the CD-ROM drive is reading data from the disc surface. For convenience, the calculations are based on the access to one data block (2,048 bytes) by the CD-ROM drive when the drive controller electronics must perform access to both the SRAM 124 and the DRAM 140. The access frequency of the controller electronics to the memories 124 and 140 are calculated as a basis of statistics and comparison.
Here it should be noted that the calculations are based on the scope of CD-ROM of the ISO 9660 standard. All the calculations are based on the worst-case considerations of read/write accesses in the memory devices when reading errors of RS codes under the 9660 standard may arise and error correction procedures must be performed. However, as may be appreciated, it is absolutely abnormal to detect error in every access to the CD-ROM disc under normal conditions. Nonetheless, as persons skilled in the art should all agree, design of the controller electronics for a CD-ROM drive must consider the worst-case conditions within the design specification.
Based on the above assumptions and in accordance with the normal procedure, the access frequency to the internal SRAM 124 by the read access controller 120 is calculated to be 3,136 accesses per data block: EQU Data input: 98.times.32=3,136.
Thus, for each data block (98 data frames of 32 bytes each), the EFM demodulator 122 sends out a total of 3,136 bytes of data to the CIRC decoder 123. CIRC decoder 123 then stores these data in SRAM 124 for performing the C1 word (referred to as C1 hereafter) de-interleaving and error detection on the CIRC-coded data. EQU C1: 98.times.(32+2.times.2)=3,528.
At the stage of the C1 word, data in each frame is processed in the following manner:
An RS code syndrome of the 32 bytes are first read, error contained therein detected and error value determined. PA1 Errors are then corrected. Normally C1 is capable of correcting two errors, with each error value read out and the correct one written back. Therefore, the processing of every error correction involves one read and one write access of data, a total of two accesses in the memory . Since there are at most two errors allowed, therefore, a maximum total of times of read/write access is 2.times.2=4 (involving both read and write).
From the above, it is clear that the maximum number of read/write accesses to each of the data frames is 36 (32+2.times.2), while there are a total of 98 frames , therefore, a total of 3,528 SRAM accesses are maximum at the C1 stage. Then, at the C2 (C2 word stage, referred to as C2 hereafter) stage: EQU C2: 98.times.(28+2.times.4)=3,528.
In comparison to the (32, 28) RS code at the C1 stage, the RS code at the C2 stage is a (28, 24) RS code, with a 28-byte input data. Since C1 relays erasure bit to C2, therefore, C2 is capable of resolving four errors at most. Similarly to the case of C1, each error requires one read operation and one write operation to complete an error correction.
Thus, for C2, each data frame requires a maximum of 36 (28+2.times.4) accesses in the SRAM. And, for the 98 total data frames, a maximum of 3,528 (98.times.(28+2.times.4)) read/write accesses in the SRAM can be expected.
After the C1 and C2 stages of error correction processing, only 24 bytes of data in the 32 bytes in each data frame are required to be relayed to the decoder. As a result, a maximum total of 2,352 accesses in the 98 data frames are expected: EQU Data output: 98.times.24=2,352.
To summarize, when a CD-ROM drive is accessing a data block on the data surface of a disc, a maximum of 12,544 accesses in the SRAM 124 as performed by the read access controller 120 can be expected: EQU 98.times.32+98.times.(32+2.times.2)+98.times.(8+2.times.4)+98.times.24=12,5
For the signal decoder 130, the access to its external DRAM 140, under conditions the same as those for the read access controller 120, can be analyzed as follows: EQU Data input: 2,340.
In accordance with the ISO/IEC 10149 standard, other than the synchronization patterns and headers, a total of 2,340 bytes out of the 2,352 bytes sent by the read access controller 120 are required to be input to the DRAM 140. EQU P subcode: 2.times.(43.times.26+2.times.1.times.43)=2,408.
The P subcode is obtained by organizing into two sets of RS codes each containing 43 groups (26, 24) based on the MSB (most significant bit) and the LSB (least significant bit) thereof. For each (26, 24) RS code, if one error were to be corrected, 2.times.1 read/write accesses would be required against the DRAM external to the signal decoder 130. Thus, there are a total of 2,408 read/write accesses: EQU 2.times.43.times.(26+2.times.1)=2,408.
The first number 2 in the above expression indicates the fact that there are MSB and LSB, two sets of data. 43, on the other hand, stands for the fact that there are a total of 43 (26, 24) RS codes. 26 indicates that there are 26 data in each RS code, and 2.times.1 represents that both read and write accesses are required to perform error correction. EQU Q subcode: 2.times.26.times.(45+2.times.1)=2,444.
The Q subcode is also divided into two sets each containing 26 groups of (45, 43) RS codes based on the MSB and LSB thereof. In a similar manner, for each (45, 43) RS code to have an error corrected, two accesses of read and write must be performed in the DRAM. Therefore, similarly to the case of the P subcode, the total number of accesses in the DRAM is then 2,444: EQU 2.times.26.times.(45+2.times.1)=2,444,
and EQU EDC: 2,068.
In accordance with the ISO/IEC 10149 standard, an EDC is composed of 2,068 bytes, therefore, a total of 2,068 accesses to the DRAM are necessary. EQU Data output: 2,048.
When finally arriving at the bus, interface controller retrieves the 2,048 bytes of data from the DRAM and controls their output.
To summarize, signal decoder 130 has a maximum of 11,308 accesses in the external DRAM 140 when the CD-ROM drive is accessing one data block over the disc storage surface: EQU 2,340+2.times.43.times.(26+2)+2.times.26.times.(45+2)+2,068+2,048=11,308.
Based on the above analysis calculations, if the read access controller 120 and the signal decoder 130 were to be merged and fabricated as a single IC device, and all the data accesses in the internal SRAM 124 are to be redirected to the external DRAM 140 instead, (in other words, if the internal SRAM 124 were to be discarded from the read access controller 120,) then the total number of memory accesses as the CD-ROM drive is reading one data block would be simply the sum of the accesses in both the SRAM 124 and the DRAM 140. A total of 23,582 access in the DRAM 140 would have to be performed if the SRAM 124 were removed: EQU 12,544+11,308=23,852.
For DRAM 140, this increase is a virtual doubling of access frequency.
Therefore, if the read access controller 120 and the signal decoder 130 of a conventional CD-ROM drive control electronics were to be integrated into one single IC chip, and the original accesses toward the SRAM 124 internal to the read access controller 120 redirected to the DRAM 140 external to the signal decoder 130, a serious problem would arise. This problem would be caused by the fact that DRAMs are inherently much slower than SRAMs. If, in the case of the conventional CD-ROM drives, the SRAM 124 in the read access controller 120 is simply discarded and its accesses redirected to DRAM 140, the bandwidth of the memory access in the DRAM is never going to meet the need of a CD-ROM drives of ten or more times of the standard single-speed drive. In other words, high-speed DRAM must be used if the internal SRAM was to be discarded. Otherwise, data transfer bottleneck forms at DRAM. It is, however, well known that high-speed DRAMs are expensive.